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Showing posts from January, 2012

Bootloader for DE-2 board with OpenRISC

The last days have been filled with a lot of Verilog and ModelSim, so I thought it would be nice with some softer programing for a change.After spending more time than I care to admit on hunting down the architecture reference guide (it is here if you need it) I figured I could as well write the bootloader that my OpenRISC platform will require. Since I haven't written anything about what I have in mind, here is a quick overview what I'm looking at creating: Implement OpenRISCMake the platform fit the DE-2 board from TerasicIt must be able to boot LinuxIt would be awesome if I can get the DM9000 network controller workingThat is the very formal (hmm) requirement specification I have in mind.Anyhow, to boot Linux on the DE-2 platform I would need to have a big RAM (hence the SDRAM controller) of a couple megabytes at least. I would also need to have some permanent storage to boot from; the flash memory will be good for that I think.When booting Linux the kernel expect that it …

Basic SDRAM controller for Terasic DE2 board

I think I pulled this one off quite nicely. The following is a controller for the 8 Megabyte SDRAM that the DE2 board uses.Features: Basic command queue ("run this when possible")Read / write supportAutomatic refreshGotchas: Uses burst of only one word, it is in other words quite slowHardcoded to work with 50 MHz and CAS 2The controller is very very simple and always executes the read and write operations as pre-charge variants which will close the activated row after the operation. The result of this is that a single read of 2 bytes will take 5 clock cycles (activate, read, CAS 2, actual read) - a write will take 3 (activate, write, recovery).I'm inclined to create something more intelligent, faster and using the other features that this SDRAM module has to offer - but this will do for now.

SDRAM is my friend

I read a lot of blogs about people doing hardware work just as I like to do. A long time ago a person who I have the utmost respect for failed to create a SDRAM (or DRAM, I can't really recall) controller which made me sure that I wouldn't be able to do it.In order to continue with OpenRISC I will need some sort of big RAM, and after a slight nudge from a friend of mine I began reading about the SDRAM my DE2 board ships with.Two days of tinkering produced this ugly (but working!) FSM. It is locked to using row 0x0 but writes a pattern to each column address (there are 256 of them on this SDRAM). After the write it will jump to a read / refresh loop which basically proves that it is capable of holding on the data.Pretty neat, this will make a great start for a SDRAM controller.